With rapidly growing popularity of handheld devices and emerging technology of internet of things, miniaturization and low power consumption are in high demand for integrated circuit (IC) in these devices. Low voltage design for these integrated circuits is necessary to achieve the goal of low power consumption. Yet a high voltage pulse is required to program or erase the data content stored in EEPROM (Electrically Erasable Programmable Read-Only Memory) and flash memory, and the high voltage pulse needs to be generated from a low voltage power supply to those devices. EEPROM and flash memory are able to maintain their data content even their power supply is turned off, and the data can be stored in the memories for a long time. These nonvolatile memory devices (both floating gate and charge trap based circuits) are broadly used in many electronics nowadays, in which a charge pump circuit is usually designed to perform the task of providing the high voltage pulses from a low voltage power supply.
FIG. 1 illustrates a classic Dickson charge pump circuit. In this circuit, NMOS transistors are constructed on P type silicon substrate and are connected as diodes. Each stage of the charge pump is formed by a diode or a diode-like device plus a capacitor. A number of the stages can be connected in serial and driven by two-phase clock signals to boost the output voltage to a level that is substantially higher than the supply voltage. Although the circuit is simple and can be readily implemented, it suffers from the body effect or substrate effect, which is defined as degradation of the threshold voltage due to a common connection of the substrate of NMOS transistors to the ground. The body effect is especially severe for latter stages of the pump with a higher boosted output voltage. Thus charge transfer efficiency is greatly reduced.
There are various methods in the art to alleviate the body effect. For example, NMOS transistors can be isolated in a deep n-type well as illustrated in FIG. 2. In this example, an NMOS transistor is formed inside a p-well 230 which is contained in a deep n-well 220 on p-type substrate 210. U.S. Pat. No. 6,914,791 is directed to an improved charge pump with each stage 200 isolated within its own deep n-well 220 that is electrically isolated from deep n-wells of other stages. However, this approach requires additional processes and complexity in device fabrication. It also raises concerns about parasitic bipolar effect related leakage or latch-up, and therefore it is not broadly used for implementation.
In another approach, charge transfer is controlled by transistor switches with precise on/off characteristics to direct charge flow. FIG. 3 illustrates a modification to Dickson charge pump, generally called CTS (Charge Transfer Scheme). In CTS charge pump, NMOS transistor M0 is a main switch. NMOS transistor M3 is an auxiliary switch which is in parallel with M0. NMOS transistor M1 together with PMOS transistor M2 forms a controlling element to M3. During the phase to turn on M3, the controlling element can pass next stage's higher output voltage to M3's gate terminal to boost its transfer efficiency. In CTS, however, the existence of PMOS transistor M2 complicates the layout and introduces the parasitic bipolar effect.
FIG. 4 illustrates another modification to Dickson charge pump, called “4-phase non-overlap clock boosting scheme”. In this design, NMOS transistor circuit is used as shown in FIG. 4. NMOS transistor M2 is a transfer switch in stage 2. In order to generate the required high voltage, the charge stored in capacitor Cd1 is transferred to the capacitor Cd2 of stage 2 through the switch, M2. To prevent undesired voltage drop across switch M2, a boosting circuit must be used so as to reduce the switch on-resistance. The boosting function is realized by NMOS transistor M2′, which is connected in between drain and source terminals of M2, and to capacitor Cb2.
FIG. 5 shows “4-phase non-overlap clock” that is used by some charge pump implementation such as illustrated in FIG. 4, or the like. When CLK3 is low, Cd1 is charging. At the same time, CLK2 is high to boost capacitor Cb1 and to fully turn on transistor M1 and ensure high conductance of M1 transistor. In this scheme, the so called “4-phase non-overlap clock” needs to be carefully designed and fine tuned to ensure its functionality, therefore its performance is sensitive to fluctuation of the supply voltage and process variation. Also, Cb's recharge period squeezes M1's turn-on period, shortening M1's effective turn-on period. In addition, the circuit implementation is complex.